Intel & AMD Unite on APX — The Biggest x86 ISA Upgrade Since 64-Bit

[Theo Gottwald]

Intel & AMD Unite on APX — The Biggest x86 ISA Upgrade Since 64-Bit


Posted by: Theo (Admin)
Date: July 2026
Category: Compiler Development / Architecture News


Hey fellow compiler builders and low-level enthusiasts,

There has been a lot of buzz around the next big x86 instruction set extension, and after doing thorough research across the latest Intel specs, GCC/LLVM patches, and AMD announcements, I wanted to put together a clear summary of where things stand. This is especially relevant for us as we maintain the PBXB64 compiler toolchain.


🚀 What Is APX?

APX (Advanced Performance Extensions) is the most significant update to the x86 instruction set architecture since the original AMD64 extension to 64-bit mode. Announced by Intel in July 2023, it is now formally being standardized across both Intel and AMD through the x86 Ecosystem Advisory Group (EAG).

The core of APX is expanding the general-purpose register file from 16 to 32 registers (RAX–R15 plus the new R16–R31, also called EGPRs). This is accomplished through a new REX2 prefix and an extended EVEX prefix for promoted instructions.


📋 What APX Brings (The Full Feature List)

• 32 General-Purpose Registers (R16–R31) — Doubles the register file, reducing memory traffic.
• NDD (New Data Destination) — Three-operand integer instructions (e.g. ADD R3, R1, R2 without destroying a source).
• NF (No Flags) — Suppress status-flag writes on common instructions to reduce dependencies.
• PUSH2 / POP2 — Push or pop two registers in a single memory operation, speeding up prologue/epilogue code.
• CCMP / CTEST — Conditional compare and test instructions that reduce branch mispredictions.
• ZU (Zero-Upper) — SETcc instructions write the full 64-bit register, eliminating pre-zeroing moves.
• JMPABS — A new 64-bit absolute direct jump for better branch prediction.
• Promoted Legacy Instructions — AADD, AAND, AOR, AXOR, BEXTR, BZHI, MULX, and many others gain EVEX forms with EGPR access.

💡 Why This Matters (Real Advantages)

According to Intel's published compiler studies, code compiled with APX delivers:

~10% fewer load instructions
~20% fewer store instructions
Similar code density despite longer prefixes (fewer instructions overall)
Lower dynamic power (register access is cheaper than memory access)

For us as compiler developers, this means our backends will eventually be able to:
- Keep more live values in registers without spilling
- Reduce expensive push/pop sequences around calls
- Eliminate unnecessary flag dependencies
- Turn more branches into predicated instructions

All of this is backward-compatible — APX code can freely call legacy code and vice versa. The new R16–R31 registers are defined as caller-saved (volatile), so legacy ABIs are preserved.


🤝 AMD + Intel: It's Official

For years, x86 ISA fragmentation has been a headache. Intel ships AVX-512, AMD skips it. AMD ships certain extensions, Intel has its own. With APX, that changes.

AMD's Corporate VP of Architecture and Strategy, Robert Hormuth, confirmed in August 2025:

"The x86 Ecosystem Advisory Group has reached consensus on... APX — next generation general-purpose instruction set extensions that boost throughput while keeping code portable across client, workstation and server CPUs."

This is not an Intel-only extension. Both vendors have agreed to implement it. This is a huge deal for compiler writers — we can target APX knowing it will run on both Ryzen and Core Ultra processors in the future.


⚠️ Reality Check: Hardware Availability

Here is the important part, and I want to be completely transparent about this:

NO APX-capable CPU is shipping today.

• Intel's Granite Rapids (Xeon 6, shipping now) does NOT include APX.
• Intel's Diamond Rapids (Xeon 7) — the first platform confirmed to include APX — has been officially delayed to 2027.
• AMD's Zen 5 (Ryzen 9000 / EPYC Turin) does NOT include APX.
• AMD's Zen 6 (EPYC Venice, expected 2026) has NOT been confirmed to include APX. Zen 6's design likely predates the EAG agreement, so APX may not arrive until Zen 6+ or Zen 7.

In other words, the earliest confirmed APX hardware is Intel Diamond Rapids in 2027. AMD's implementation could be 2027 or later.


🛠� Toolchain Support Is Already Here

The good news: the software ecosystem is ready well ahead of the silicon.

GCC 14	EGPR, PUSH2/POP2, NDD, PPX via -mapxf
GCC 15	Full APX: CCMP, CTEST, NF, ZU, JMPABS
LLVM/Clang	EGPR + NDD merged; full APX in progress
Binutils 2.42	APX linker relocations
Linux 6.16+	Kernel APX support; KVM guest patches underway
glibc 2.39	PLT rewrite with JMPABS for better branch prediction

This means compiler developers can already experiment with APX code generation, even if they have no hardware to test it on yet.


🔧 What This Means for PBXB64 (and Projects Like It)

For our own compiler toolchain (and any other x86-64 compiler project), here is the roadmap reality:

• APX is a multi-month engineering effort to implement properly. It requires new register classes, new prefix encoders (REX2, extended EVEX), and new instruction tables.
• You cannot validate APX code on real hardware today. You need CPU emulation (Intel SDE) or a simulator.
• Because APX is standardized across both vendors, any effort you invest now will pay off on both Intel and AMD chips in 2027+.
• Legacy x86-64 code will run unchanged on APX-capable CPUs, so there is no rush to migrate.

My recommendation: Start by reading the Intel APX specification (Intel APX ISA Spec) and monitor the GCC/LLVM patches to understand the encoding rules. But do not commit to a full APX backend until at least one vendor's silicon is confirmed and available for testing. The spec is stable, the encoding is documented, but hardware validation is still ~18+ months away.


📌 Summary

APX is real. Both AMD and Intel have agreed to standardize it.
APX is significant. 32 GPRs, 3-operand instructions, conditional compares, and more.
APX is not here yet. Earliest confirmed hardware: Intel Diamond Rapids in 2027.
APX is backward-compatible. No legacy code needs to change.
APX toolchains are ready. GCC 15, LLVM, Linux, and glibc already support it.

If you have questions about APX encoding, the REX2 prefix, or how it might fit into a compiler backend, drop them below. I'll update this thread as new silicon announcements come in.

Cheers,
— Theo


Sources: Intel APX Architecture Specification (355828), GCC 15 APX patches, LLVM EGPR/NDD RFC, AMD Robert Hormuth x86 EAG statement (August 2025), Intel Computex 2026 Diamond Rapids announcement, Tom's Hardware / The Register reporting.